As the high integration of a semiconductor device progresses, a size of the gate/source/drain electrodes of a MOS transistor is reduced, resulting in a reduction in channel length. When the channel length is reduced, short channel effects (SCE) and reverse short channel effects (RSCE) are generated so that it is very difficult to control the threshold voltage of the transistor.
Also, since the driving voltage is relatively high over the size of the high integrated semiconductor device, electrons implanted from the source are severely accelerated due to the potential gradient state of the drain, and hot carriers are generated at the vicinity of the drain. A lightly doped drain (LDD) has been introduced in the art to improve the structural vulnerability of the semiconductor device.
FIG. 1 is a cross-sectional view showing a semiconductor device having a LDD structure in accordance with the related art.
Referring to FIG. 1, an active region of a substrate 10 is defined by a device isolating layer, and a gate electrode 13 of a polysilicon material and a gate insulating film 12 are patterned.
Then, the active regions at both sides of the gate electrode 13 are implanted with ions to form an LDD region 14. A sidewall spacer 18 of a silicon dioxide (SiO2) material is formed at sides of the gate electrode 13.
The sidewall spacers 18 can be formed with spacers 15 of a silicon nitride (SiN) material, wherein the sidewall spacer 18 functions a role of mitigating interlayer stress and improving adhesion between the spacer 15 and the gate electrode 13.
Finally, the active regions at both sides of the spacer 15 can be implanted with ions to form a source region 16 and a drain region 17.
When forming the spacer 15 and sidewall spacer 18, deposition, etching, and cleaning processes are performed, resulting in a complicated procedure and increased manufacturing time and cost.
Also, the deposition process for forming the spacer 15 is performed at a high temperature for a long time so that the distribution of the ions implanted into the LDD region 14 occurs, which may degrade the characteristics of the device.
That is, when forming the LDD region 14, the ions, such as B and BF, are implanted and are diffused toward the edge of the channel region by the heat treatment process when forming the spacer 15.
Therefore, the LDD region 14 is extended into the semiconductor substrate below the edge of the gate electrode 13. If the overlap of the LDD region 14 and the gate electrode 13 occurs, the overlap capacitance of the gate-drain is increased and the RC delay is increased so that the electrical characteristics of the semiconductor device, including operating speed, are degraded.
Since the semiconductor device includes the implant layers, such as the source region, the drain region, and the LDD region, there is a limitation for minimizing the size of the semiconductor device. In addition, there are problems in several processes, and there is a limitation for improving operation reliability.